The present invention relates to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit for quickly processing broadband data signals, and a manufacturing method such a semiconductor integrated circuit.
Recently, as a highly information signal processing has been demanded, an IC (integrated circuit) capable of processing signals at high speed has been needed. In order to realize a higher speed operation of ICs, in order to realize high integration transistors used the ICs, they have been formulated in highly performance quality and advanced by shortening interconnect lengths to reduce interconnect delay time of the ICs.
High performance of an element can be obtained by basically reducing the size of the element. For example, in the case of a field effect transistor, by reducing a gate length, and in the case of a bipolar transistor, by reducing a base thickness and an emitter width, a current gain cut-off frequency is improved and by reducing peripheral parts, a parasitic capacitance is reduced, thereby realizing more powerful transistors.
As the transistors have been miniaturized and high performed, there is a problem with a parasitic capacitance of the interconnect within a chip arises, and thus a possibly short distance layout between elements by a micro-manufacturing and high integration using multi-layered interconnect have been proposed.
In FIG. 1, there is shown a conventional emitter coupled logic (ECL) circuit as a fundamental logic circuit using bipolar transistors. This ECL circuit comprises a current switch circuit (differential circuit) and an emitter follower circuit.
The current switch circuit is a circuit that emitters of a pair of driving transistors 603 and 604 are connected in common. Both of the emitters of the driving transistors 603 and 604 are connected to a collector of constant current source transistor 607 in common. Collectors of the transistors 603 and 604 are connected in common to a connection line via a pair of load resistors 605 and 606, respectively and a high level power supply terminal 608 is coupled to the connection line.
The emitter follower circuit comprises a pair of input transistors 612 and 613 and a pair of load resistors 614 and 615. The bases of the two input transistors 612 and 613 are connected to the collectors of the two drive transistors 603 and 604, respectively. The emitters of the two input transistors 612 and 613 are commonly linked to the emitter of the constant current source transistor 607 via the respective load resistors 614 and 615 and a connection line and this connection line is coupled to a low power supply terminal 609. The collectors of the two input transistors 612 and 613 are connected in common to the connection line coupled to the high level power supply terminal 608. Two output terminals 616 and 617 of the ELC circuit are connected to the respective connection lines connecting the emitters of the input transistors 612 and 613 and the load resistors 614 and 615, respectively.
In this ECL circuit, with high performance of each transistor, the high integration is realized by shortening the interconnect between the current switch circuit and the emitter follower circuit and the interconnect within these two circuits in order to reduce interconnect delay time are shortened to intend the high integration. As a result, the high speed operation of the ECL circuit can be realized.
In recent years, a signal speed of the data to be used has become a high frequency such as GHz order and in such a high frequency band, the influence of the high frequency has not been considered up to this time but cannot become ignored even in the shortened interconnect, interconnect length of several tens of xcexcm to several hundreds of xcexcm. For example, in a distribution constant model of interconnect, propagation time xcfx84 (sec/m) is expressed as follows;
xcfx84={square root over ( )}LC(=(LC)1/2) 
In this formula, L is inductance of interconnect and C is capacitance of the interconnect. From this formula, it is found that with the rise of the data signal speed such as GHz order (or about 1 GHz or more), it is necessary to reduce the values of L and C. Furthermore, when the load capacitance of the interconnect increases, the rising of the data signal is delayed, which leads to problem of the delay and the inability of the signal propagation.
In order to reduce the delay time, a circuit using air-bridge interconnect having a low parasitic capacitance is known. However, owing to an inductor component of the interconnect, distortion occurs in the data signal even within the circuit. As one example, in FIG. 2, there is shown a two-stage ECL circuit constituting two current switch circuits and four emitter follower circuits.
In FIG. 2, the two-stage ECL circuit includes the first ECL circuit having two inputs and outputs shown in FIG. 1 and the second ECL circuit having a similar construction to the first ECL circuit. The outputs of the first ECL circuit are input to the second ECL circuit via two interconnects 638 and 639. In the first ECL circuit shown in FIG. 2, the same members as those shown in FIG. 1 are designated by the same numerals and thus the explanation thereof can be omitted.
The second ECL circuit includes one current switch circuit and one emitter follower circuit in the same manner as the first ECL circuit. In this case, the emitter follower circuit of the first ECL circuit is called the first stage emitter follower circuit and the emitter follower circuit of the second ECL circuit is the second stage emitter follower circuit.
In the second stage emitter follower circuit includes a pair of input transistors 616 and 617 and a pair of load resistors 618 and 619. More specifically, the base of the input transistor 616 is coupled to the connection line connecting the emitter of the input transistor 612 of the first emitter follower circuit and the load resistor 614 via the interconnect 638, and the base of the input transistor 617 is coupled with to the connection line connecting the emitter of the input transistor 613 of the first emitter follower circuit and the load resistor 615 via the interconnect 639. The emitters of the two input transistors 616 and 617 are connected in common to a connection line via the respective load resistors 618 and 619, and this connection line is coupled to the low level power supply terminal 609. The collectors of the two input transistors 618 and 619 are connected in common to a connection line to which the high level power supply terminal 608 is coupled.
The current switch circuit of the second stage ECL circuit, in the same manner as the first ECL circuit, includes a pair of drive transistors 623 and 624, a constant current source transistor 627 and a pair of load resistors 625 and 626. The emitters of the two drive transistors 623 and 624 are commonly coupled with the collector of the constant current source transistor 627. The base of the drive transistor 623 is connected to the connection line connecting the emitter of the input transistor 616 and the load resistor 618, and the base of the drive transistor 624 is connected to the connection line connecting the emitter of the input transistor 617 and the load resistor 619. The collectors of the two drive transistors 623 and 624 are connected in common to the connection line via the respective load resistors 625 and 626, and this connection line is coupled to the high level power supply terminal 608. The emitter of the constant current source transistor 627 is linked to the connection line to which the low level power supply terminal 609 is coupled.
In the two stage ECL circuit, like the ECL circuit shown in FIG. 1, the current switch circuit and the emitter follower circuit are connected by the interconnect and the transistors and the resistors within the circuits are connected by the interconnect. However, only the interconnects 638 and 639 coupling the first emitter follower circuit with the second emitter follower circuit will now be considered.
FIG. 3 shows a cross sectional view of the interconnects 638 and 639 for coupling the first and the second emitter follower circuits of the conventional two-stage ECL circuit. The back surface of a semiconductor substrate on which the ECL circuit is formed, is an ground 630. A interconnecting layer of Au such as the interconnects 638 and 639 having a thickness of 1 xcexcm and a width of 6 xcexcm is formed on the ground 630 via a semiconductor layer 631 of a GaAs layer having a thickness of 120 xcexcm. A interconnect length of the interconnecting layer is 500 xcexcm.
In FIG. 4, there is shown a frequency characteristic of from DC to 50 GHz gain of the aforementioned two-stage ECL circuit. Although the interconnect length between the first emitter follower circuit and the second emitter follower circuit is shorter than a wavelength of a quarter of 50 GHz, since the length of the interconnects 638 and 639 is 500 xcexcm, it is found that the gain peaking around 27 GHz.
When a data signal having a pseudo-random pattern of 20 Gbit/sec shown in FIG. 5 is input to the two-stage ECL circuit, as its output waveform is shown in FIG. 6, distortion comes about in the data signal by the interconnects 638 and 639 having the interconnect length of 500 xcexcm and hence none of the amplification and propagation of the correct data signal can be carried out.
In the actual interconnect, R, L and C components are included and the resistance components of the L and C are expressed by jxcfx89L and jxcfx89C. When the speed of the data signal is fast, the value xcfx89 becomes large, and thereby its influence is large even when the L and C are small. Hence, when the speed of the data signal becomes fast, a mismatch arises in the impedance between the interconnect and its front stage circuit or the interconnect and its post stage circuit. The afore-mentioned gain peaking and the distortion of the data signal are mainly caused by this impedance mismatching.
When the impedance mismatching occurs between the interconnect and its front stage circuit or the interconnect and its rear stage circuit, the reflection of the signal is caused at the mismatching part. By this reflection, overshoot (or undershoot) or a ringing is caused in the signal waveform and the signal waveform is disturbed. Further, a problem of the delay by this reflection, for example, the delay of the rise time due to the signal reflection arises.
As described above, the frequency becomes higher (the interval between rising time and the fall time of the data signal become shorter), the characteristic impedance of the shortened interconnect is necessarily considered. However, heretofore, since the characteristic impedance of such a interconnect has not been considered conventionally, when the frequency becomes high, the distortion of the data signal or the gain peaking of the frequency characteristic occurs and the data signal cannot be propagated well.
In Japanese Patent Laid-open Application No. Hei 9-162653, a high frequency differential output circuit includes a differential pair of field effect transistors and a constant current circuit of a field effect transistor, and further includes an inductive circuit for preventing a parasitic capacitance of the field effect transistor from affecting a bad influence to an impedance characteristic of an output terminal by an inductive impedance of the inductive circuit. However, in this case, additional interconnect for connecting the inductive circuit to the field effect transistor is necessary and it becomes disadvantageous to realize high integration and low cost.
In Japanese Patent No. 2842463, in order to reduce reflection of a transmission signal generated at a part that an impedance of interconnect coupling electronic circuits is discontinuously changed, for example, a part that a interconnect width is narrowed, a reflection reduction circuit including a first resistor connected between the interconnect and a power source potential and a second resistor connected between the interconnect and an earth potential is placed near the impedance discontinuously changing part of the interconnect. However, in this case, the reflection of the signal at the discontinuous part of the interconnect can be reduced, but the aforementioned problem of the reflection caused by the impedance mismatching between the interconnect and its front stage circuit or between the interconnect and its rear stage circuit cannot be solved.
It is therefore an object of the present invention to solve the afore-mentioned problems of the prior art and to provide a semiconductor integrated circuit and a method for producing a semiconductor integrated circuit, which is capable of preventing an occurrence of distortion of a data signal and a gain peaking of a frequency characteristic.
In accordance with one aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first circuit having an output terminal; a second circuit having an input terminal; and interconnect for connecting the output terminal of the first circuit and the input terminal of the second circuit, a characteristic impedance of the interconnect matching an output impedance of the first circuit in a predetermined frequency range.
The semiconductor integrated circuit of the present invention can further comprise an impedance converter circuit connected between the interconnect and the output terminal of the first circuit.
In accordance with another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first circuit having an output terminal; a second circuit having an input terminal; and interconnect for connecting the output terminal of the first circuit and the input terminal of the second circuit, a characteristic impedance of the interconnect matching an input impedance of the second circuit in a predetermined frequency range.
The semiconductor integrated circuit of the present invention can further comprise an impedance converter circuit connected between the interconnect and the input terminal of the second circuit.
In accordance with another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first circuit having an output terminal; a second circuit having an input terminal; and interconnect for connecting the output terminal of the first circuit and the input terminal of the second circuit, a characteristic impedance of the interconnect matching both an output impedance of the first circuit and an input impedance of the second circuit in a predetermined frequency range.
The semiconductor integrated circuit of the present invention can further comprise a first impedance converter circuit connected between the interconnect and the output terminal of the first circuit and a second impedance converter circuit connected between the interconnect and the input terminal of the second circuit.
In a semiconductor integrated circuit of the present invention, the predetermined frequency range includes a frequency that distortion is caused in a waveform of a data signal propagating the interconnect by either an inductor or capacitance of the interconnect.
In a semiconductor integrated circuit of the present invention, the characteristic impedance of the interconnect is determined so that an eye opening ratio representing a rate of an amplitude size of an eye pattern of a data signal propagating the interconnect to the amplitude size of the eye pattern of the data signal input to the output terminal of the first circuit may be larger than a predetermined value.
In a semiconductor integrated circuit of the present invention, assuming that the output impedance of the first circuit, the input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formulas in a frequency range for the data signal propagating the interconnect.                                           "LeftBracketingBar"                                                                                Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            -                                                R                  2                                                                      R                    1                                    +                                      R                    2                                                                        "RightBracketingBar"                     less than                                     1              -              M                        2                          ⁢                  
                ⁢        and                            (        1        )                                          "LeftBracketingBar"                                                                                          Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            ⁡                              [                                  1                  +                                                                                                              R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                      *                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          1                                                +                                                  R                          2                                                                                                                    ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        2        )            
In a semiconductor integrated circuit of the present invention, assuming that the output impedance of the first circuit, the input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formula in a frequency range for the data signal propagating the interconnect.                               "LeftBracketingBar"                                                                      Z                  0                                                                      Z                    0                                    +                                      R                    1                                                              ⁡                              [                                  1                  +                                                                                    R                        2                                            -                                              Z                        0                                                                                                            R                        2                                            +                                              Z                        1                                                                                            ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        1        )            
In a semiconductor integrated circuit of the present invention, assuming that the output impedance of the first circuit, the input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formula in a frequency range for the data signal propagating the interconnect.                               "LeftBracketingBar"                                                                                          Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            ⁡                              [                                  1                  +                                                                                                              R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                      *                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          1                                                +                                                  R                          2                                                                                                                    ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        2        )            
In a semiconductor integrated circuit of the present invention, the interconnect, the first circuit and the second circuit are formed on a same semiconductor substrate to obtain the semiconductor integrated circuit having a monolithic structure.
In accordance with another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit, comprising the steps of forming a first circuit having an output terminal and a second circuit having an input terminal on a semiconductor substrate; and forming interconnect for connecting the output terminal of the first circuit and the input terminal of the second circuit, a characteristic impedance of the interconnect being determined so that an eye opening ratio representing a rate of an amplitude size of an eye pattern of a data signal propagating the interconnect to the amplitude size of the eye pattern of the data signal input to the output terminal of the first circuit may be larger than a predetermined value.
In a method for producing a semiconductor integrated circuit of the present invention, assuming that an output impedance of the first circuit, an input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formulas in a frequency range for the data signal propagating the interconnect.                                           "LeftBracketingBar"                                                                                Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            -                                                R                  2                                                                      R                    1                                    +                                      R                    2                                                                        "RightBracketingBar"                     less than                                     1              -              M                        2                          ⁢                  
                ⁢        and                            (        1        )                                          "LeftBracketingBar"                                                                                          Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            ⁡                              [                                  1                  +                                                                                                              R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                      *                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          1                                                +                                                  R                          2                                                                                                                    ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        2        )            
In a method for producing a semiconductor integrated circuit of the present invention, assuming that an output impedance of the first circuit, an input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formula in a frequency range for the data signal propagating the interconnect.                               "LeftBracketingBar"                                                                      Z                  0                                                                      Z                    0                                    +                                      R                    1                                                              ⁡                              [                                  1                  +                                                                                    R                        2                                            -                                              Z                        0                                                                                                            R                        2                                            +                                              Z                        0                                                                                            ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        1        )            
In a method for producing a semiconductor integrated circuit of the present invention, assuming that an output impedance of the first circuit, an input impedance of the second circuit, the characteristic impedance of the interconnect and the eye opening ratio are R1, R2, Z0 and M, respectively, these values can satisfy the following formula in a frequency range for the data signal propagating the interconnect.                               "LeftBracketingBar"                                                                                          Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            ⁡                              [                                  1                  +                                                                                                              R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                      *                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          1                                                +                                                  R                          2                                                                                                                    ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        2        )            
The method for producing a semiconductor integrated circuit of the present invention can further comprise forming an impedance converter circuit connected between the interconnect and the output terminal of the first circuit, and it is assumed that the output impedance, converted by the impedance converter circuit, of the first circuit is R1.
The method for producing a semiconductor integrated circuit of the present invention can further comprise forming an impedance converter circuit connected between the interconnect and the input terminal of the second circuit, and it is assumed that the input impedance, converted by the impedance converter circuit, of the second circuit is R2.
In general, a characteristic impedance of interconnect and an output impedance and an input impedance of circuits constituting a semiconductor integrated circuit can be known by calculations (simulation). For example, the characteristic impedance of the interconnect can be calculated on the basis of its width, thickness, dielectric constant and the like. As described above, according to the present invention, the characteristic impedance of the interconnect is adapted to match the output impedance of the first circuit, the input impedance of the second circuit, or both the output impedance and the input impedance of the first and the second circuits in a predetermined frequency range (the frequency that the distortion is caused in the waveform of the data signal propagating the interconnect by the inductor or capacitance of the interconnect, more specifically, the frequency of the order of GHz), and thus none of the distortion of the data signal and the gain peaking can be caused. Further, the inductive circuit mentioned in the Japanese Patent Laid-open Publication No. 9-162653 is not necessary. In particular, in the case that the characteristic impedance of the interconnect is set so that an eye opening ratio may be larger than a predetermined value, the occurrence of the distortion in the data signal waveform owing to the reflection can be exactly prevented.
Furthermore, assuming that an output impedance of a first circuit, an input impedance of a second circuit, a characteristic impedance of interconnect and an eye opening ratio of a data signal (pulse signal) propagating the interconnect are R1, R2, Z0 and M, respectively, it is found from various experimental results up to this time that when these values satisfy at least one of the following two formulas in a frequency range for the data signal propagating the interconnect,                                           "LeftBracketingBar"                                                                                Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            -                                                R                  2                                                                      R                    1                                    +                                      R                    2                                                                        "RightBracketingBar"                     less than                                     1              -              M                        2                          ⁢                  
                ⁢        and                            (        1        )                                          "LeftBracketingBar"                                                                                          Z                    0                                                                              Z                      0                                        +                                          R                      1                                                                      ⁡                                  [                                      1                    +                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                                      ]                                            ⁡                              [                                  1                  +                                                                                                              R                          2                                                -                                                  Z                          0                                                                                                                      R                          2                                                +                                                  Z                          0                                                                                      *                                                                                            R                          2                                                -                                                  Z                          0                                                                                                                      R                          1                                                +                                                  R                          2                                                                                                                    ]                                      -                                          R                2                                                              R                  1                                +                                  R                  2                                                              "RightBracketingBar"                 less than                               1            -            M                    2                                    (        2        )            
the matching between the characteristic impedance of the interconnect and at least one of the output impedance of the first circuit and the input impedance of the second circuit can be made and an occurrence of distortion in the waveform of the data signal propagating the interconnect owing to reflection caused by an impedance mismatching can be prevented and a good data signal transmission can be performed. The formula (i) mainly restricts a size of overshoot, caused by the reflection, of the data signal waveform and the formula (ii) mainly restricts a size of undershoot, caused by the reflection, of the data signal waveform. In the present invention, an open state of an aperture of an eye pattern of the data signal waveform can be set to a certain range by using the formulas (i) and (ii) so that the data signal may be propagated. Hence, the occurrence of the distortion of the data signal waveform owing to the reflection can be exactly prevented.